Open to opportunities

Advika
Metre

MS Computer Engineering at NC State University

Specializing in |

Building efficient hardware from the ground up.

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Education

Where I've studied

NC State University

MS Computer Engineering · 2025–2027

GPA 3.89 / 4.0Raleigh, NC

Relevant Coursework

Parallel ComputingASIC & FPGA DesignMicroprocessor ArchitectureASIC Verification (SystemVerilog)Advanced Microarchitecture

RCOEM, Nagpur

BTech Electronics Engineering · 2021–2025

GPA 9.42 / 10India

Activities & Societies

🗣️Reader's Reverie Literary Club🎭Nautanki - The Drama Club⚙️Technical Club

Highlights

→3× National Debating Finalist/Semi-Finalist
→2× Cultural Excellence Awardee
→10+ Finalist/Semi-Finalist in Inter-Intra Collegiate Debating
→Hosted and Participated — Reverie Unplugged Podcast
→Managed and Hosted events for 200+ participation

Experience

Where I've worked

Research Intern — Memory Built-In Self-Test

Electronics Department, RCOEM

Nov 2024 – May 2025

→Designed and implemented Verilog FSM BIST for March C- and Checkerboard on Xilinx Artix-7, with built-in fault injection; added a parallel hybrid flow using dual-port BRAM to increase test throughput.
→Reduced the LUT count by 22% and the power consumption while effectively addressing limitations in detecting complex in-transition and stuck-at faults.

Summer Intern — Ecostruxure Development

VNIT

June 2024 – July 2024

→Configured Schneider Ecostruxure IIoT panels with AR-enabled devices to stream equipment telemetry for remote diagnostics and faster issue resolution.
→Used SoMove, Augmented Operator Advisor, Machine Expert, and Secure Connect to program, integrate, and troubleshoot deployed systems.

Projects

What I've built

🧪

I2C Multi-Bus Controller Verification

ASIC VerificationSystemVerilog

Layered SystemVerilog verification environment for an I2C multi-bus controller with scoreboard-based checking.

🧠

CNN Accelerator with DRAM Interface

RTL DesignVerilog

Complete CNN inference pipeline streaming directly from DRAM with custom memory controller.

⚡

Superscalar Pipeline Simulator

CPU ArchitectureC++

Configurable out-of-order superscalar CPU simulator with full pipeline modeling.

🔗

Bus Based Cache Coherence Protocols

Multi-core SystemsMemory ConsistencyC++

Adaptive MOESI coherence variant evaluated on 16-core SMP simulations.

💾

Cache and Memory Hierarchy Simulator

CPU ArchitectureC++OOP

Flexible L1/L2 cache simulator with WBWA policy, LRU replacement, and stream buffers.

Skills

What I know

Languages

CC++PythonVerilogSystem VerilogCUDA

Tools & Platforms

VivadoLinuxModelsimLTSpice

Concepts

FSMRTL DesignComputer ArchitectureDigital DesignCache CoherenceStatic Timing AnalysisDFTTestbench DevelopmentMemory BISTTesting and Verification

Blog

What I write

HardwareAIThermodynamics

The Thermodynamics of Intelligence: A Hardware Reality Check

We are leaving the phase of 'peak performance' and entering the phase of thermodynamic constraints. Intelligence in silicon is no longer capped by calculation speed but by the energy cost of moving information.

Jan 15, 2026·5 min read

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Achievements

What I've earned

📄

IEEE Conference Paper

"FSM Based Implementation of March C- and Checkerboard Algorithm", presented at IEEE 6th International Conference for Emerging Technology (INCET), Belagavi, India, 2025.

🏆

National Debating Finalist

3× National Debating Finalist — IIT Madras, IIM Indore, VNIT — 2024, 2023, 2022.

Contact

Let's connect

asmetre@ncsu.edu

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AdvikaMetre